Thread: mem bus
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Old 20th December, 2005, 12:50 PM
Aedan Aedan is offline
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Join Date: September 2001
Location: Europe
Posts: 13,075

Originally Posted by yogurt_21
shoot I ran my asus A7V880 with 4x256 (geil ddr 400 cl2.5-4-4-8)at 1T and you're saying an nvidia 939 chipset has an inferior memory contoller than a 462 via chip?
The nVidia socket 939 based solutions shouldn't have a memory controller at all, as it's integrated on the CPU! There are issues running all memory banks (as opposed to DIMM banks) full at 1T - basically the memory controller on the CPU struggles to manage the timing.

The prime reason for this is that each bank of memory adds a bit extra load. When you have eight banks, the CPU doesn't have enough strength to drive all eight banks at 1T. Obviously this depends on just how much extra power each bank of memory requires to drive it. Memory that provides less of a load is more likely to run happily at higher speeds.

Also remember that as there's no latency between the memory controller and the CPU core, the memory controller can issue commands to the RAM faster than a system with a front side bus between the CPU and memory controller. Thus memory that works ok on an older FSB based system might struggle to keep up on a system where the memory controller is on the CPU.
Any views, thoughts and opinions are entirely my own. They don't necessarily represent those of my employer (BlackBerry).
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