| Interesting, but, looking at POWER6.
POWER6 has two memory controllers, which fits with Opteron sockets. POWER6 has an onboard 32MB L3 cache controller, but the cache itself is off chip. POWER7 would either have to integrate it or dispose of it.
Opteron has four hypertransport links. POWER6 uses three links to provide interconnectivity within a node (a node consists of four processors), and two links to connect to the second level system structure. That gives a node eight connections to other nodes. Currently these links are designed so that they run at 8bytes for every other cycle of the processor frequency. As they're combined links, they provide 67% data transport and 33% coherence information. That means they can move 67% of 40B of data per every other cycle. How well that fits into Hypertransport, I don't know.
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