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Old 21st November, 2002, 02:13 PM
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Some thoughts about nForce2 pci lock

I have been doing alot of thinking lately and come up whit a thing.

In the nforce2 chip-set the SPP(northbrigde) and the MCP(southbridge) i connected whit a 800mhz hypertransport bus.

The SPP is responsible for the memory interface, Front-side buss to the cpu and the APG port. In all the manuals i have read about nforce2 it says that the fsb can be changed by the user and so can the agp bus. The agp bus is also able to lock the the speed to 66MHz.

The MCP handles the PCI,SOUND, IDE, and so on. Ther is no documentation of a pci divider or pci lock.

Now to the thinking i have done.

What if there is no need of a divider or pci lock. Perhaps the PCI bus is always 33MHz. The SPP and the MCP is connected via the 800MHz HT-bus. so why change the speed of the PCI when you change the FSB och AGP bus. All you have to do is use a clock generator running independently fom the AGP, FSB.

ET got really upset when people started to ask questions of a pci lock and 1/6 divider. Maby he got mad because there is no lock or divider and he is under a NDA and cant tell us how it works.

AMD showed Bartons running att 200MHz FSB lately running on a nForce2 board. Why would the do that if the chip-set canĀ“t handle it?
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Old 21st November, 2002, 02:32 PM
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Perhaps a pic can help. Copied from Epox manual(sorry i had to)

My writing i red.
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Some thoughts about nForce2 pci lock-nforce2.jpg  
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Old 21st November, 2002, 03:53 PM
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I understand what you're saying. The question is whether a second clock generator is indeed utilized. If that is indeed the case, then I can see how the PCI can be set at a fixed speed. The setup above is nothing new really. The northbridge on all the current VIA chipsets is basically memory controller and AGP controller with everything else dumped into the southbridge. Basically, it comes down to whether the chipset itself can support a second clock.
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Old 21st November, 2002, 04:03 PM
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after reading some more info i have come to the conclusion that nForce2 doesnt use a external clockgenerator.

With no externl clock gen. i se abslute no problem of implementing a locked PCI.

"Interesting to see that all three companies stick exactly to the specifications. One reason for this is that the nForce2 chipset does not require an external clock generator. "

sorry for qoting THG...

Some coments please?
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Old 21st November, 2002, 05:53 PM
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Assuming that Hypertransport is running async at the SPP, and it's buffered through a BiFIFO or something similar, then I don't see why you can't run the blocks at different clocks.

After all, the PCI spec is designed to be independant of the rest of the host system. As such, it shouldn't have to rely on the clock generator for it's own bus... Except perhaps for cost.

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