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Old 31st August, 2005, 03:44 AM
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Question Effective L3 on AMD X2 ???

Ran across a discussion raising the idea that a significant reason why a larger L2 benefits the AMD X2 relatively less than the Intel Dual is that an AMD core is able to indirectly address the adjacent core's L2 which can then function as an L3. This discussion acknowledged the fact that the AMD L1 and L2 are exclusive, whereas the Intel are not, but the L3 consideration was entirely separate from that.

Anybody able to corroborate this aspect of the X2 design and whether it actually comes to play with currently available software?
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Old 31st August, 2005, 01:14 PM
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I don't think they can use the cache like that I think it's more that if they are both working on something from the same section of memory then they can use one anothers cache instead of duplicating data
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Old 1st September, 2005, 12:23 AM
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AMD's Athlon XP processors were designed from the the ground up with an eye toward dual-core operation. It's said that they are a good deal better in dual-core configuration than Intel's hurriedly slapped together double core efforts.

A large L3 cache has to be a good thing. Yet I remember that almost the only reason that the Athlon XP stole a two year march on the Pahntium family was because AMD quadrupled the processor's L1 cache in relation to the tight-butted, archaic 16kb L1 from Intel. Intel might still be giving us a splendiferous 16kb if their Israeli branch didn't see the light and address this rediculous state of affairs in the Pentium M. I wonder if Intel will redesign this near fatal flaw in P4's?
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Old 1st September, 2005, 12:52 AM
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A large L3 cache can't compensate for a small L1 cache. The best thing would be to have all of the cache be dedicated to L1. Unfortunately, this is very expensive in terms of power, which is why CPUs tend to have a small L1 and a rather larger L2. I understand that there is some flirtation by Intel with a large L3, though. However, the relatively large L1 cache on the Athlons is the reason why large L2 isn't as much of a help to Athlons as it is with the P4 chips.

As to the original question, both CPU cores have to implement bus snooping to maintain cache coherency. Because of this, if the data that one core needs happens to reside in the other core's cache, then the data request from the 1st core will be serviced by the cache of the second core, in effect creating an L3 cache. However, this cache will be of only very limited benefit, as it is unlikely in the vast majority of situations to even occur. Windows (and, I would assume, most other multi-cpu aware OSen) tends to try to run a thread on the same CPU it ran on last, in order to take advantage of any data that may in the cache. Since most of the data a thread manipulates are on the thread stack, this tends to mean that a given core will generally run a given thread.
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