Athlon X2...with shared L1?

[cadaveca]

here she be folks(taken from AMD website):

AMD Athlon 64 X2 Dual-core Details
Processor AMD Athlon 64 X2 Dual-core
Model 4400+
Ordering P/N (Tray) ADV4400DAA6CD
Ordering P/N (PIB) ADA4400CDBOX
Operating Mode 32/64
Stepping E6
Frequency 2200Mhz
HT Speed 2000
Voltage 1.35-1.40 V
Max Temp 71°C
Thermal Power 89W
L1 Cache 128KB
L2 Cache 1MB x2
CMOS Technology 90nm SOI
Socket Socket 939

please note the standard X2 listings for the same cpu on AMD website:

AMD Athlon 64 X2 Dual-core Details
Processor AMD Athlon 64 X2 Dual-core
Model 4400+
Ordering P/N (Tray) ADA4400DAA6CD
Ordering P/N (PIB) ADA4400CDBOX
Operating Mode 32/64
Stepping E6
Frequency 2200Mhz
HT Speed 2000
Voltage 1.35-1.40 V
Max Temp 65°C
Thermal Power 110W
L1 Cache 128KB + 128KB
L2 Cache 1MB x2
CMOS Technology 90nm SOI
Socket Socket 939



Did you spot the difference?

ADV4400DAA6CD =128k L1
ADA4400DAA6CD =128k + 128K L1

AMD site compare

I'm attempting to get my hands on one right now. more to follow...

[madcatmk3]

that will seem interesting.

[Gizmo]

I dunno. Shared L2 cache might make sense. But shared L1? It is quite unlikely in most situations that the two cores are going to be running enough of the same code to make shared L1 worthwhile. At least, it would seem that way to me.

[cadaveca]

you got a good point, giz, however i think the missing cache would make for a dualcore tha had lower power requirements, and then might go further in clocking. It gives you almost hte same thing as a hyperthreaded P4, but with one heck of a lot more functionality.

[SteveI]

VERY INTERESTING!!!
Lower power, 89w v 110w, and higher Max temp 71c v 65c.

This could get really good.. same stepping E6 tho..

[cadaveca]

Deal is these aren't in retail yet in force...but they will be.

less power requirements but higher max temps....you know what's holding the X2's back from scaling.

[Aedan]

Originally Posted by cadaveca

ADV4400DAA6CD =128k L1
ADA4400DAA6CD =128k + 128K L1

That makes absolutely no sense whatsoever. Having a shared L1 cache isn't very clever, but have a shared L1 cache and two seperate L2 caches makes zero sense. Remember data cascades down through the caches, so a shared L1 cache would also imply a shared L2 cache. Without reworking parts of the caching mechanism (and inducing latency), there isn't any way for the L1 cache to know which processor the data came from to split out into an L2 cache.

I think it's either a typo (IE, shared L1, shared L2) or a typo (IE, seperate L1, seperate L2).

Or AMD moved to harvard architecture, but I think we'd realise that very quickly!

[cadaveca]

SteveI already caught it Aedan. was jsut an attention-getter. the cpu is only lower power-consumption, with higher rated temps.

like OSA, OSK, OSE opterons.

[Aedan]

Darn, there I was hoping that AMD had seen the light and decided that they were moving to a Harvard architecture. That would be awesome for speeding up data processing operations!