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Old 27th June, 2006, 08:19 PM
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AMD Reverse HyperThreading

Conroe is almost upon us, with bulk shipments comming later in the year, leaving AMD with an old, yet good platform to work with in the AM2 K8. Could it be though, that AMD has found something to turn their now 3 year old architecture, still used in the Athlon X2, into the monster needed to keep Conroe at bay?

http://www.theinquirer.net/?article=32589

Quote:
THE LAUNCH OF Intel Conroe is scheduled to go on July 23rd, when partners will start rolling out the new products. The NDA for reviews is scheduled to expire around July 28th.

However, AMD has a counter-attack weapon hidden in its Socket AM2 infrastructure.

It seems that all AM2 CPUs were outfitted with a support for Reverse-HyperThreading, an architectural change which enables software to think that it is working on a single-core alone. By combining two cores, the company has been able to produce the six IPC "core" that will go head to head against four IPC "core" from Conroe/Merom/WoodCrest combo.

It seems that in certain cases, even an old AMD Athlon 64 3800+ can wipe the floor with Core 2 Duo E6300 CPU.

As we all know - the results from E6700 and X6800 against FX-62 will be nice, but the real fight with AMD is the one for the Conroe with 2MB of L2 cache. The system memory avoidance technology is working flawlessly on a 4MB cache model, but the case is reversed in the two Meg cache variant, especially in cache-hit sensitive apps, such as games.

In single-treaded apps, Core 2 Duo is expected to struggle against Reverse HyperThreading CPUs, which work at higher clock frequencies and produce higher instruction per clock ratios (IPC).

AMDs Reverse-HT is a dynamic technology, and with Microsoft's Windows update and a new processor driver, the driver will copy the graphics drivers of today's 3D accelerators. The driver will detect the app, see if it is multithreaded or not and turn the ReverseHT on, or leave it off. µ
Now this isn't just from Inq. I've seen this popping up everywhere for the last few weeks. Could it be that this keeps the blue army at bay until K8L?
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Old 27th June, 2006, 08:28 PM
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Would open a few eyes around here! How really very sneaky of AMD! ":O}
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Old 27th June, 2006, 08:32 PM
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I was just thinking that this was pretty sneaky. Kept thier cards hidden untill the final call....

Love it..
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Old 27th June, 2006, 09:26 PM
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Would be interesting to see if this effect is something in any way limited to AM2 platforms, or if it applies to older Athlon X2 CPUs as well. Imagine having that kind of a boost in single thread intensive games etc.
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Old 27th June, 2006, 10:17 PM
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Quote:
Originally Posted by dsio
Would be interesting to see if this effect is something in any way limited to AM2 platforms, or if it applies to older Athlon X2 CPUs as well. Imagine having that kind of a boost in single thread intensive games etc.
Admittedly I don't really understand this new feature from AMD, yet I don't see how it could work with older K8 processors. If this is a new kick adze feature, bully for AMD!
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Old 27th June, 2006, 10:29 PM
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"Architectural change" ----Really? hmm wierd.
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Old 28th June, 2006, 12:36 AM
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Very impressive. This will keep gamers on AMD's side. Still, in multitasking or dual core optimized programs the Conroe still has an advantage over the X2s, but in games and single thread apps the X2s will pretty much mop the floor with the Conroes, or so it seems. I'll wait until all of the benches come out before I draw any conclusions.

Though it does seem if I'd waited for the X2 price drops, I would've been rewarded. I decided on my single core for 1) Price and 2) Gaming. The X2s will be great for gaming....so I guess I just missed it. It always seems like you get something that you think will be great for what you do, and then right afterwards something else comes out at the same price that's 50% better than the one you just got.
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Old 28th June, 2006, 12:46 AM
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I think it may give AMD an advantage against the 2mb low end version, but I just don't see it making too much of a difference in high. And why is theinq the only source?!

Take a look at the fundamental differences in architecture in the link below.

http://hkepc.com/hwdb/x6800vsfx62-5.htm
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Old 28th June, 2006, 04:00 AM
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A lot of the literature I've read on this seems to suggest that it is just speculative multi-threading (which is like speculative execution on steroids).

Basically, super-scalar CPUs (pretty much anything built in the last 10 years) look at the instruction stream and figure out which instructions have data dependencies on other stuff in the pipeline. Instructions that don't have dependencies on each other can be run through the execution units in parallel, thus allowing the execution engine to more efficient, executing multiple instructions at the same time. If the pipeline guesses wrong and there IS a data dependency, the results from the instruction involved get thrown away, and the instruction gets re-executed with the correct data. The reorder buffer handles this magic.

Building on that idea, then, you expand the concept to look at entire code paths and determine if the entire path can be split off into its own execution thread. A good example of where this could occur is with modular code, where a function handles one particular thing. If the inputs and outputs of the function are well defined, it could be possible to make a guess as to what those would be for a given state in the program, and execute the function on another thread (or CPU), and have the results ready when needed. This would effectively allow the hardware to make a single-threaded application into a multi-threaded one, without the software developer doing anything.

Intel has been experimenting with this for a while with their Mitosis project, and I understand that something like it has been implemented in the world of big iron for a while now.

I'm not entirely convinced this is what AMD is doing. For one thing, all previous approaches to this problem that I have researched involved the COMPILER doing the code analysis. The reason for doing this is simple; the amount of code that must be analyzed can be rather large, and a significant amount of the information required to make intelligent decisions about what can and can not be parallelized would only be readily available from the source code, I would think. In addition, for this to be of any value in a CPU, it has to be very FAST, and also not use up a lot of transistors (say a million or so, tops). I admit that I'm not an expert here, but I'm not convinced that this code analysis can be achieved in hardware without incuring significant memory bandwidth overhead.

That being said, I suppose it IS possible that the code analysis is actually being done by the CPU driver that has been mentioned, and is occuring at the time the application is loaded. Were that the case, it might be feasible.

I dunno. And that's the problem; there's just a lot I don't know.
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Old 28th June, 2006, 04:41 AM
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A lot less than I don't know. ":O}
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Old 28th June, 2006, 05:39 AM
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A lot less than I don't know. ":O}
same!!
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Old 28th June, 2006, 11:46 AM
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Well AMD, for a long time, were known for their advantages in games (or something like that) and gamers have generally gone for AMD as their platform of choice. This 'new architecture' will help keep gamers happy. However, unless it is a feature that was present in the older cores, and can be coded into games, only the newer cores will be able to show off just how good it is. AMD had predicted a bad year ahead once the new intel cores were released, looks like they had an acxe up their sleeve the whole time. Question is, what's it like against a Yonah core?
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Old 28th June, 2006, 11:58 AM
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Yonah has been superceeded by Conroe.
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Old 29th June, 2006, 01:28 AM
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Old 29th June, 2006, 02:21 AM
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Quote:
Originally Posted by skool h8r
Well AMD, for a long time, were known for their advantages in games (or something like that) and gamers have generally gone for AMD as their platform of choice. This 'new architecture' will help keep gamers happy. However, unless it is a feature that was present in the older cores, and can be coded into games, only the newer cores will be able to show off just how good it is. AMD had predicted a bad year ahead once the new intel cores were released, looks like they had an acxe up their sleeve the whole time. Question is, what's it like against a Yonah core?
By my understanding, this can be applied at a software level in the form of a driver for any Athlon X2 CPU. All this really is, is a hack to make a dual core 3 execution unit CPU appear to be a single 6 execution unit CPU.

In a way, it would kind of be working in a similar way to alternate frame rendering in SLI. Both cores working on the same job, taking turns on the load to split it up.
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Old 29th June, 2006, 02:38 AM
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Quote:
Originally Posted by gizmo
I'm not convinced that this code analysis can be achieved in hardware without incuring significant memory bandwidth overhead.
Perhaps this bandwidth has been afforded by the move to DDR2?
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Old 29th June, 2006, 02:53 AM
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Quote:
Originally Posted by Favu
Perhaps this bandwidth has been afforded by the move to DDR2?
I rather doubt it, as the 'bandwidth' is IMHO, a fictitious fabrication on the part of an industry that can no longer sell us truly better products, but only products that are PERCEIVED as 'better'.
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Old 29th June, 2006, 10:31 AM
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Quote:
Originally Posted by dsio
By my understanding, this can be applied at a software level in the form of a driver for any Athlon X2 CPU. All this really is, is a hack to make a dual core 3 execution unit CPU appear to be a single 6 execution unit CPU.
Thought that the Athlon 64/Opteron architecture had 9 execution units? That is, three ALUs, three address generators and three floating point units. That ignores the interesting double dispatch operations the pipelines can provide.

I don't think that a software driver on it's own would be able to provide any level of hack that would increase performance. The simple fact of having to handle the re-ordering and register moves between cores in software would chew up a lot of CPU time. The driver would have to work out what order the cores would execute the instructions in to ensure that it could synchronise register contents between the two cores. That would not be a trivial task at all as far as I can understand.
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Old 29th June, 2006, 02:44 PM
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Old 29th June, 2006, 08:16 PM
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Any chance of such a veiwing?
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