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Old 2nd March, 2007, 07:04 AM
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IBM to Ditch SRAM for Embedded DRAM on Power CPUs

According to a presentation that chip designers from IBM made recently at the IEEE's annual International Solid State Circuits Conference in San Francisco, the company has perfected a way to embed Dynamic RAM, or DRAM--the normal kind of main memory used in computers--into microprocessors rather than having to resort to the much more transistor-intensive Static RAM, or SRAM, commonly used in on-chip L1 and L2 cache memories.

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Old 2nd March, 2007, 08:46 PM
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I'm kind of confused.
Isn't the whole idea of SRAM on the CPU as means of cache much faster than using DRAM?
I thought the static part of the RAM in SRAM was pretty important. Just to add the accociativity and set accociativity? Also its easy and fast reading and writing ?

I can understand the transistor saving, but there has to be a performance advantage to it as well. Or is it because they save in transistor count that they can then use those "spare" transistors for more functionality?
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Last edited by Wolf2000me; 2nd March, 2007 at 08:46 PM.
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Old 2nd March, 2007, 09:31 PM
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Up until this development, SRAM has been, at a minimum, an order of magnitude faster on access times than DRAM. Modern DRAM can transfer data at a rate competitive with SRAM, but that first access cycle is a killer on DRAM; even the fastest DRAM has a first cycle penalty of about 40 nS, whereas even slow SRAM has a first cycle penalty of about 10 nS, and the fastest SRAM can get into the 800 pS range.

However, there is a big problem with SRAM, and that problem is that the only way to implement an SRAM is to build what is essentially a 'D'-type flip-flop or 'latch' circuit, and you have to use at least 6 transistor gates to do that (also known as 6T SRAM). There are some deisgns that have implemented a 'psuedo-SRAM' with 4 transistors, but they use special processing tricks, and pay a performance penalty to do so. As a consequnce of the 6 gate requirement, SRAM consumes a lot of space for on cell. Build 512K of those cells, or 1Meg of those cells, and you have chewed up a LOT of real-estate for storage. Now factor in the fact that switching those transistors uses a lot of power, and simply HAVING all of those transistors results in a lot of leakage, and you have power and heat issues along with space issues.

DRAM is slower than SRAM, but also uses less space. The thing that makes it slower is also the thing that allows it to consume less space - the storage capacitor. A DRAM memory cell can be implemented using just one transistor gate and one storage capacitor per cell. Although the capacitor will be about twice the size of the transistor, you still realize a net space savings of about 2:1 compared to SRAM. Unfortunately, you also take a performance hit of around 10:1 or worse, and you have to bulid 'refresh' circuitry to keep the cell from losing its mind. See, the problem with the capacitor is that it tends to leak charge over time; the smaller the capacitor, the less charge it has to leak, and so the faster it tends to lose its mind. The job of the refresh logic is to periodically read that memory cell, and write its contents back into the cell, thus restoring the charge; 'refreshing' it. Because of this refresh process, you periodically lose the ability to access that cell. Modern design techniques allow us to 'hide' this refresh behind another memory access in most cases, but it is still there.

There is another big advantage of DRAM over SRAM, and that is power consumption; because DRAM uses 1/5 the transistors of SRAM and capacitors don't generate heat, DRAM uses less power - a LOT less.

Note that NONE of this has to do with the associative-ness of the cache, which is a completely separate design issue.

The trick that IBM has come up with, allows them to build a DRAM cell that is only about twice as slow as SRAM (instead of an order of magnitude slower). Since DRAM can be made in about have the space of SRAM, this means that IBM can increase the amount of cache by a factor of two, and offset the performance penalty of the slower cache in most applications (because quite often the CPU cache doesn't have the data it needs, and is waiting for main memory, which is many orders of magnitude slower than the cache).

Ok, so we've made the memory cell half the size, but we need twice as many. So what have we gained? We are still using the same amount of space, right?

Well, it turns out that it may not be necessary to actually use twice as much cache to achieve the same effect. However, even if we do, the big thing we gain is POWER savings. Remember that we are only using 1 transistor, rather than 6. That means a HUGE savings in power.

Sorry to be so long winded, and I hope that this explanation clears things up for you a bit?
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Old 3rd March, 2007, 03:38 PM
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Yeah it does, thanks for enlightening me

Now that I'm thinking about it. Some years ago I heard about the development of another type of DRAM. This one based on the Flash technology, with major advantage its self sustainability without the need for refreshing the data. The only problem I heard was its producing price and performance that wasn't yet groundbreaking.
Did you hear anything about that? And why not use flash DRAM instead of SRAM?
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Old 3rd March, 2007, 06:28 PM
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Flash is not DRAM or SRAM. It is a memory storage technology based on entirely different principles, and those principles are what makes it so slow.

There are two basic problems with Flash for high-performance applications:
1) It takes a long time to store information, because of the fact that a floating gate has to be charged to a certain potential, and that charging process is not only very slow, but really can't be accellerated very much.
2) There is a limit on the durability of the cells; you can only write data to them so many times, and as process technologies get smaller, the durability suffers. There is some speculation that 45 nM may be the smallest process that will be able to be used for manufacturing Flash, unless some exotic materials are used, which will drive up the cost.
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Old 3rd March, 2007, 07:42 PM
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Yeah I figured it wouldn't be DRAM.

I know EPROM or EEPROM had a very limited durability, like in 100000 fetch and store procedures before being deionized. So the same is true for Flash then, however probably more durable. But yeah, I figure even if it would be a 100 times more durable it wouldn't nearly be durable enough for internal memory usage.
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Old 3rd March, 2007, 08:14 PM
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EPROM, EEPROM, and Flash are all variations of the same basic technology.

The primary difference between Flash and the older EPROM, and EEPROM technologies, is that Flash erases and programs an entire block of memory (usually 2KiB or 4KiB) at one time in parallel, while EPROM and EEPROM program one byte at a time. The gate oxide thickness has been reduced for Flash to allow for faster programming but there is no reason the same thing couldn't be done for EPROM or EEPROM, since (as I said) they are all variations of the same basic technology.

Last edited by Gizmo; 3rd March, 2007 at 08:15 PM.
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