Innovation Silicon, Inc. and Z-RAM

[Gizmo]

Lost Circuits has an interesting interview with Jeff Lewis, VP of Worldwide Marketing at Innovation Silicon, about their new memory technology, Z-RAM. Rather like the Rambus folks, ISi is in the business of licensing technology, not building chips. However, unlike Rambus, this technology looks like it might actually be able to make a difference to the computer world in a positive way: it promises to double memory capacity on a given process technology over what is available today in standard DRAM, while also being easier to manufacture.

So, what do you think? Is this the wave of the future, or is it destined to be another niche product, like Rambus? Tell us!

[benighted]

Sounds great. But if RAM doesn't really need capacitors, why build it with them in the first place? How is the memory actually stored without them? the article didn't really explain that

[cadaveca]

Neat stuff, but very similar to the Xbox360 design...i wonder if the two are related. No capacitors are needed as the transistors effectly act as capacitors themselves, if i got it right. I didn't read the linked atricle tho, so i could be totally off.

[benighted]

From what I can tell a capacitor stores a charge but a transistor just turns it on and off.

[Gizmo]

Originally Posted by benighted

From what I can tell a capacitor stores a charge but a transistor just turns it on and off.

A basic principle of electronics is that ALL devices have an inherent capacitance, inductance, and resistance. Devices are constructed to emphasize one or more of the characteristics while minimizing others, but they exist in all devices. As a device becomes smaller, capacitance and resistance begin to become significant issues to deal with.

Most RAM is constructed in one of two ways; either you construct a flip-flop circuit using 6 transistors (6T SRAM), or you construct a charge reservoir and and sense amplifier (1T capacitor). The flip-flop has the advantage that it is very, very fast, and stable; once you store a value in it, that value remains until you change it or lose power (hence the term 'static' RAM). It can also be manufactured using standard semiconductor processes. It has the disadvantage that it is very large in terms of chip real-estate, because it requires 6 transistors (or 4, in some very imaginative designs). The charge reservoir has the advantage that, even though it requires a capacitor, it can be made smaller than the flip-flop because it only requires one transistor to read the capacitance charge, instead of 4 or 6. As a consequence, it generally enjoys a 2x density advantage over even the 4T designs. The disadvantage is that parasitic leakage causes the capacitor to lose charge over time, so it has to be 'refreshed'. In addition, the act of reading the charge actually destroys the charge, so you have to have feedback circuits to replenish the charge after a read. As a consequence, it is considered rather volatile (hence the term 'dynamic' RAM). It also requires specialized processing, because capacitor manufacturing processes are not too friendly to semiconductors.

So, how does Z-Ram fit in? Well, basically, the fair-haired boys in the ISi labs realized that, with SOI, the Floating-Body effect essentially turns the transistor into a usable capacitor. This effect exists with all CMOS processes, but is exploitable with SOI because of the exceptional insulation characteristics of the process, AIUI. This allowed them to get rid of the independent charge reservoir, and let the sense transistor serve as its own capacitor.

Bear in mind that this is all based on my own (limited) understanding of the processes involved, so I may have a few of the details wrong, but that is the general gist of it. Except that Cad managed to put it a bit more succinctly.

BTW, Cadaveca, what do you mean about being similar to the Xbox360 design?

[cadaveca]

The XBOX360 has 10MB of emdedded SOI DRAM, kinda acting as an L2 or L3 cache for the ATI GPU/memorycontroller. This buffer, and the speed of SOI-ram(as well as less latency), interfaces directly with the cpu cluster and the 512mb of DDR3.

[Gizmo]

Originally Posted by cadaveca

The XBOX360 has 10MB of emdedded SOI DRAM, kinda acting as an L2 or L3 cache for the ATI GPU/memorycontroller.

Really? I dinae know this. That's interesting. I knew that AMD had a license to use the tech in one of their up-coming chips, but I was unaware of this. Very interesting.

I would imagine access times to the RAM would improve somewhat with this technology, but I tend to doubt that they are in the realm of what you can achieve with fast SRAM. Have you heard?

[Gizmo]

Also, I thought it interesting that in the interview they were willing to talk about the fact that they can achieve a 2x density improvement, and the manufacturing process is easier, but they won't discuss power consumption without an NDA. That makes me think it is either very, very good, or else it just absolutely stinks. What do you think?

[madcatmk3]

Originally Posted by gizmo

. That makes me think it is either very, very good, or else it just absolutely stinks. What do you think?

Probly bad otherwise they would have simply said it and made it all hyped up.

[Gizmo]

Originally Posted by madcatmk3

Probly bad otherwise they would have simply said it and made it all hyped up.

With SOI, it could go either way, and that may be why the NDA; the power dissipation figures could be highly dependent on the SOI 'secret sauce'.

[madcatmk3]

your malking me hungry gizmo

[benighted]

Very informative gizmo. Now if only I could remember all that.

[cadaveca]

Originally Posted by gizmo

With SOI, it could go either way, and that may be why the NDA; the power dissipation figures could be highly dependent on the SOI 'secret sauce'.

Based on what i see for other SOI implementations @ current nodes, the problem's not there to begin with, in regards to density. Of course, the implentation kinda says that SOI-ram requires a heatsink, but not a very large one.

Look at the power implementations on the x1k cards...which uses SOI for a few integral parts, passively cooled.

Then look @ L1/L2/L3 caches of any cpu...basically the same thing as well...and VERY fast.

Depends on yeild...as how i look at it, they could be using the edges of cpu masks, where there are not complete dies, to increase profitability of every slice of silicon that goes through the fab, and this becomes even more important with the increase of die size, even while node size drops.

Originally Posted by gizmo

Really? I dinae know this. That's interesting. I knew that AMD had a license to use the tech in one of their up-coming chips, but I was unaware of this. Very interesting.

I would imagine access times to the RAM would improve somewhat with this technology, but I tend to doubt that they are in the realm of what you can achieve with fast SRAM. Have you heard?

Here'sa start for ya, with some old info:

Memory Bandwidth:
22.4 GB/s memory interface bus bandwidth
256 GB/s memory bandwidth to EDRAM
21.6 GB/s front-side bus

Originally Posted by TEAMXBOX

Today, NEC Electronics has confirmed that Microsoft will incorporate leading-edge embedded DRAM (eDRAM) technology from NEC Electronics in the Xbox 360. The high-performance eDRAM macros designed by NEC Electronics are a key piece of the graphics subsystem and will enable the console to provide users with a stunning high-definition graphics experience.

In a world exclusive, TeamXbox was the first publication to reveal the existence of the embedded video RAM back in February, 2004. Last week, we also revealed the ATI patent for a “method and apparatus for supporting anti-aliasing oversampling in a video graphics system that utilizes a custom memory for storage of the frame buffer.” In layman terms, that is embedded video RAM for the GPU to use it as a frame buffer.


The eDRAM graphics chip is manufactured in NEC Electronics' 300-millimeter (mm) wafer fabrication facility, which runs the company's most advanced processes.

"The next-generation Xbox platform will provide gamers with a highly advanced graphics experience," said Todd Holmdahl, corporate vice president, Xbox Product Group. "NEC Electronics' cutting-edge embedded DRAM technology plays a vital role in enabling our graphics engine's performance, while its manufacturing process provides a reliable resource that can deliver the volumes required to support what will be an extremely popular gaming platform."

"Microsoft's next-generation Xbox platform promises to be a revolutionary gaming platform and must-have consumer device," said Hirokazu Hashimoto, executive vice president, NEC Electronics Corporation. "NEC Electronics is pleased to be an integral part of this device and looks forward to working with Microsoft to make the next-generation Xbox platform a top seller."

Microsoft wants to eliminate current graphics architectures' bottlenecks and this embedded DRAM solution is the key to enable advanced visuals at high resolutions.

The name "embedded DRAM" is used because the memory is embedded directly onto a chip. The advantage of embedded RAM is that it offers a speed and bandwidth far superior to conventional out-of-the-chip memory. Think of it as comparing system memory (your computer RAM) with a microprocessor's cache memory.

Of course, this memory will be of a limited size because it is a lot more expensive than regular external memory.

The use of the embedded DRAM can be better understood when viewing the following image from the ATI patent: http://media.teamxbox.com/dailyposts...x360_edram.gif




The figure illustrates a block diagram of a “graphics processing system” that supports oversampling anti-aliasing. The system includes a graphics processor (GPU), a sample memory (the standard memory on today's video cards) and a custom memory module (the embedded RAM).

This custom memory has been created mostly to perform anti-aliasing operations and help overcome today's biggest problem in graphics: memory bandwidth. By using this embedded RAM, which is similar to a processor's cache memory, the Xbox 360 will be able to run games at 720p HDTV resolution, that is 1280x720, with full screen anti-aliasing and almost no impact on framerate.

[Gizmo]

Originally Posted by cadaveca

Memory Bandwidth:
22.4 GB/s memory interface bus bandwidth
256 GB/s memory bandwidth to EDRAM
21.6 GB/s front-side bus

Aye, but that's bus interface speed, not access times. Despite the huge increases in bandwidth that have been achieved over the last 20 years, DRAM access times (latencies) are still only about 4x better now than they were then (i.e. 40 nS, instead of 150 nS). Fast SRAM can manage 10 nS pretty easily, where that was impossible 20 years ago, unless you wanted to go to ECL, so SRAM technology has improved immensely, basically on the same scale the process technology has improved.

[cadaveca]

uh, DDR3...1.1ns not fast enough for ya? because of the stability offered by the SOI process, speeds can be ramped up much higher than current DRAM implementations. As, you surmise, power leakage @ speeds were it matters is a paramount factor, but providing cooling to deal with that leakage @ excessive speeds is not as hard as it is with current DRAM, thanks to the lovely nature of the SOI process.

What's the access time of a A64 L1? same or better available by this tech. 256GB per second isn't going to come with high access times....it's just not possible. remember that current "standard" DDR is 3200mb/second, but as clock frequncies increase, bandwidth increases; as latencies get higher, bandwidth drops tho, and in my playing around with ram i have come to realize the relationship between latencies and bandwidth all too much, so 256000mb/second is pretty damb fast!


It's the other working parts that need to catch up in thier latencies, bandwidth, and access times, not the SOI-ram implementations!