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Old 27th March, 2006, 06:54 PM
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Innovation Silicon, Inc. and Z-RAM

Lost Circuits has an interesting interview with Jeff Lewis, VP of Worldwide Marketing at Innovation Silicon, about their new memory technology, Z-RAM. Rather like the Rambus folks, ISi is in the business of licensing technology, not building chips. However, unlike Rambus, this technology looks like it might actually be able to make a difference to the computer world in a positive way: it promises to double memory capacity on a given process technology over what is available today in standard DRAM, while also being easier to manufacture.

So, what do you think? Is this the wave of the future, or is it destined to be another niche product, like Rambus? Tell us!
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Old 27th March, 2006, 07:42 PM
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Sounds great. But if RAM doesn't really need capacitors, why build it with them in the first place? How is the memory actually stored without them? the article didn't really explain that
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Old 27th March, 2006, 07:42 PM
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Neat stuff, but very similar to the Xbox360 design...i wonder if the two are related. No capacitors are needed as the transistors effectly act as capacitors themselves, if i got it right. I didn't read the linked atricle tho, so i could be totally off.
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Old 27th March, 2006, 07:54 PM
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From what I can tell a capacitor stores a charge but a transistor just turns it on and off.
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Old 27th March, 2006, 08:14 PM
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Quote:
Originally Posted by benighted
From what I can tell a capacitor stores a charge but a transistor just turns it on and off.
A basic principle of electronics is that ALL devices have an inherent capacitance, inductance, and resistance. Devices are constructed to emphasize one or more of the characteristics while minimizing others, but they exist in all devices. As a device becomes smaller, capacitance and resistance begin to become significant issues to deal with.

Most RAM is constructed in one of two ways; either you construct a flip-flop circuit using 6 transistors (6T SRAM), or you construct a charge reservoir and and sense amplifier (1T capacitor). The flip-flop has the advantage that it is very, very fast, and stable; once you store a value in it, that value remains until you change it or lose power (hence the term 'static' RAM). It can also be manufactured using standard semiconductor processes. It has the disadvantage that it is very large in terms of chip real-estate, because it requires 6 transistors (or 4, in some very imaginative designs). The charge reservoir has the advantage that, even though it requires a capacitor, it can be made smaller than the flip-flop because it only requires one transistor to read the capacitance charge, instead of 4 or 6. As a consequence, it generally enjoys a 2x density advantage over even the 4T designs. The disadvantage is that parasitic leakage causes the capacitor to lose charge over time, so it has to be 'refreshed'. In addition, the act of reading the charge actually destroys the charge, so you have to have feedback circuits to replenish the charge after a read. As a consequence, it is considered rather volatile (hence the term 'dynamic' RAM). It also requires specialized processing, because capacitor manufacturing processes are not too friendly to semiconductors.

So, how does Z-Ram fit in? Well, basically, the fair-haired boys in the ISi labs realized that, with SOI, the Floating-Body effect essentially turns the transistor into a usable capacitor. This effect exists with all CMOS processes, but is exploitable with SOI because of the exceptional insulation characteristics of the process, AIUI. This allowed them to get rid of the independent charge reservoir, and let the sense transistor serve as its own capacitor.

Bear in mind that this is all based on my own (limited) understanding of the processes involved, so I may have a few of the details wrong, but that is the general gist of it. Except that Cad managed to put it a bit more succinctly.

BTW, Cadaveca, what do you mean about being similar to the Xbox360 design?
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Old 27th March, 2006, 08:39 PM
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The XBOX360 has 10MB of emdedded SOI DRAM, kinda acting as an L2 or L3 cache for the ATI GPU/memorycontroller. This buffer, and the speed of SOI-ram(as well as less latency), interfaces directly with the cpu cluster and the 512mb of DDR3.
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Old 27th March, 2006, 10:05 PM
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Quote:
Originally Posted by cadaveca
The XBOX360 has 10MB of emdedded SOI DRAM, kinda acting as an L2 or L3 cache for the ATI GPU/memorycontroller.
Really? I dinae know this. That's interesting. I knew that AMD had a license to use the tech in one of their up-coming chips, but I was unaware of this. Very interesting.

I would imagine access times to the RAM would improve somewhat with this technology, but I tend to doubt that they are in the realm of what you can achieve with fast SRAM. Have you heard?
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Old 27th March, 2006, 10:09 PM
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Also, I thought it interesting that in the interview they were willing to talk about the fact that they can achieve a 2x density improvement, and the manufacturing process is easier, but they won't discuss power consumption without an NDA. That makes me think it is either very, very good, or else it just absolutely stinks. What do you think?
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Old 28th March, 2006, 01:50 AM
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Quote:
Originally Posted by gizmo
. That makes me think it is either very, very good, or else it just absolutely stinks. What do you think?
Probly bad otherwise they would have simply said it and made it all hyped up.
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Old 28th March, 2006, 01:57 AM
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Quote:
Originally Posted by madcatmk3
Probly bad otherwise they would have simply said it and made it all hyped up.
With SOI, it could go either way, and that may be why the NDA; the power dissipation figures could be highly dependent on the SOI 'secret sauce'.
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Old 28th March, 2006, 02:07 AM
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your malking me hungry gizmo
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Old 28th March, 2006, 02:11 AM
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Very informative gizmo. Now if only I could remember all that.
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Old 28th March, 2006, 03:18 AM
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Quote:
Originally Posted by gizmo
With SOI, it could go either way, and that may be why the NDA; the power dissipation figures could be highly dependent on the SOI 'secret sauce'.

Based on what i see for other SOI implementations @ current nodes, the problem's not there to begin with, in regards to density. Of course, the implentation kinda says that SOI-ram requires a heatsink, but not a very large one.

Look at the power implementations on the x1k cards...which uses SOI for a few integral parts, passively cooled.

Then look @ L1/L2/L3 caches of any cpu...basically the same thing as well...and VERY fast.

Depends on yeild...as how i look at it, they could be using the edges of cpu masks, where there are not complete dies, to increase profitability of every slice of silicon that goes through the fab, and this becomes even more important with the increase of die size, even while node size drops.

Quote:
Originally Posted by gizmo
Really? I dinae know this. That's interesting. I knew that AMD had a license to use the tech in one of their up-coming chips, but I was unaware of this. Very interesting.

I would imagine access times to the RAM would improve somewhat with this technology, but I tend to doubt that they are in the realm of what you can achieve with fast SRAM. Have you heard?
Here'sa start for ya, with some old info:

Memory Bandwidth:
22.4 GB/s memory interface bus bandwidth
256 GB/s memory bandwidth to EDRAM
21.6 GB/s front-side bus



Quote:
Originally Posted by TEAMXBOX
Today, NEC Electronics has confirmed that Microsoft will incorporate leading-edge embedded DRAM (eDRAM) technology from NEC Electronics in the Xbox 360. The high-performance eDRAM macros designed by NEC Electronics are a key piece of the graphics subsystem and will enable the console to provide users with a stunning high-definition graphics experience.

In a world exclusive, TeamXbox was the first publication to reveal the existence of the embedded video RAM back in February, 2004. Last week, we also revealed the ATI patent for a “method and apparatus for supporting anti-aliasing oversampling in a video graphics system that utilizes a custom memory for storage of the frame buffer.” In layman terms, that is embedded video RAM for the GPU to use it as a frame buffer.


The eDRAM graphics chip is manufactured in NEC Electronics' 300-millimeter (mm) wafer fabrication facility, which runs the company's most advanced processes.

"The next-generation Xbox platform will provide gamers with a highly advanced graphics experience," said Todd Holmdahl, corporate vice president, Xbox Product Group. "NEC Electronics' cutting-edge embedded DRAM technology plays a vital role in enabling our graphics engine's performance, while its manufacturing process provides a reliable resource that can deliver the volumes required to support what will be an extremely popular gaming platform."

"Microsoft's next-generation Xbox platform promises to be a revolutionary gaming platform and must-have consumer device," said Hirokazu Hashimoto, executive vice president, NEC Electronics Corporation. "NEC Electronics is pleased to be an integral part of this device and looks forward to working with Microsoft to make the next-generation Xbox platform a top seller."

Microsoft wants to eliminate current graphics architectures' bottlenecks and this embedded DRAM solution is the key to enable advanced visuals at high resolutions.

The name "embedded DRAM" is used because the memory is embedded directly onto a chip. The advantage of embedded RAM is that it offers a speed and bandwidth far superior to conventional out-of-the-chip memory. Think of it as comparing system memory (your computer RAM) with a microprocessor's cache memory.

Of course, this memory will be of a limited size because it is a lot more expensive than regular external memory.

The use of the embedded DRAM can be better understood when viewing the following image from the ATI patent: http://media.teamxbox.com/dailyposts...x360_edram.gif




The figure illustrates a block diagram of a “graphics processing system” that supports oversampling anti-aliasing. The system includes a graphics processor (GPU), a sample memory (the standard memory on today's video cards) and a custom memory module (the embedded RAM).

This custom memory has been created mostly to perform anti-aliasing operations and help overcome today's biggest problem in graphics: memory bandwidth. By using this embedded RAM, which is similar to a processor's cache memory, the Xbox 360 will be able to run games at 720p HDTV resolution, that is 1280x720, with full screen anti-aliasing and almost no impact on framerate.
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Old 28th March, 2006, 04:55 AM
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Quote:
Originally Posted by cadaveca
Memory Bandwidth:
22.4 GB/s memory interface bus bandwidth
256 GB/s memory bandwidth to EDRAM
21.6 GB/s front-side bus
Aye, but that's bus interface speed, not access times. Despite the huge increases in bandwidth that have been achieved over the last 20 years, DRAM access times (latencies) are still only about 4x better now than they were then (i.e. 40 nS, instead of 150 nS). Fast SRAM can manage 10 nS pretty easily, where that was impossible 20 years ago, unless you wanted to go to ECL, so SRAM technology has improved immensely, basically on the same scale the process technology has improved.
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Old 28th March, 2006, 06:36 AM
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uh, DDR3...1.1ns not fast enough for ya? because of the stability offered by the SOI process, speeds can be ramped up much higher than current DRAM implementations. As, you surmise, power leakage @ speeds were it matters is a paramount factor, but providing cooling to deal with that leakage @ excessive speeds is not as hard as it is with current DRAM, thanks to the lovely nature of the SOI process.

What's the access time of a A64 L1? same or better available by this tech. 256GB per second isn't going to come with high access times....it's just not possible. remember that current "standard" DDR is 3200mb/second, but as clock frequncies increase, bandwidth increases; as latencies get higher, bandwidth drops tho, and in my playing around with ram i have come to realize the relationship between latencies and bandwidth all too much, so 256000mb/second is pretty damb fast!


It's the other working parts that need to catch up in thier latencies, bandwidth, and access times, not the SOI-ram implementations!
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Old 28th March, 2006, 09:58 AM
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Usually it's the signalling from package to package that limits the bandwidth possible, and latencies selecting the memory address to actually read. I suspect that there's a link between the relatively small size of the L1 cache and it's speed too, in that the less multiplexing involved, the faster data can be retreived. If this is true, then one would assume that the high memory densities used for DDRx would tend to increase their latencies. Does this hold true?

Digit-Life said this for the L1 data cache on the Athlon 64 :-
Quote:
Originally Posted by Digit-life
The D-cache, data cache, is also dual-channel partially associative. In the current modification it supports 40-bit physical and 48-bit linear address, though this parameter can be increased if necessary. The data block is also 64 bytes. The added feature is MOESI protocol of operation of the L1 cache earlier used in the AMD760MP(X) chipset. It supports two 64-bit read/write operations each clock into different banks! There are three sets of tags - port A, port B, snoop. The fetch latency of this cache is 3 clocks in case of aligned addressing, and 1 clock if it is not aligned. By the way, it's quite low penalty, - in the Pentium 4 the figures are 6 to 10 clocks for unaligned data, according to different test techniques. Intel doesn't say a word about it.
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Old 28th March, 2006, 05:10 PM
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Quote:
Originally Posted by cadaveca
uh, DDR3...1.1ns not fast enough for ya?
We are confusing terms here. When I talk about access times, I'm talking about the first cycle. What you are talking about for access times is the burst rate.

I don't give a damn about what the burst rate is; that first cycle is the one that kills you. It doesn't matter that I can burst 7 cycles in 8 nS, if the first cylce takes 40 nS, meaning that the 8 cylce burst takes 48 nS, particularly if the data access pattern means that I can't use more than about 25% of the data I just bursted in (which is usually the case).

If you look at the timings for DRAM from the first SDRAM up through DDR SDRAM, they haven't done squat for the first cycle times, and they haven't done much for the latencies. All they've done is up the speed they can send the data down the bus.

Let me ask you this: If it takes 30 minutes to get on the freeway, does it really matter that once I'm on the freeway, I can get to my destination in 20 seconds? The entire trip still took over 30 minutes. If I drop the time on the freeway from 20 seconds to 10 seconds, I can claim a 50% speed improvement, but have I really changed anything? The trip still takes over 30 minutes.
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Old 28th March, 2006, 06:02 PM
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Well, that goes well beyond my scope of knowledge about this tech...as before yesterday i had never heard of z-ram...but i think that the first seek time depends on the overall size of the cache, and the efficiency of the controller, just aas much as it depends on the cache design itself.

I tihnk that the lack of such high refresh rates as are found in current ram implementations, in comparison to to current DRAM applications, as well as the higher coherency of the cache makes it much more feasable that most think....and that's why we find SOI-ram caches on FB-DIMMS, which support both DDR2 and DDR3, and witha little tweaking could support DDR4 as well. the fact that this buffer is useful accross these many techs says just how fast SOI-ram tech can be, and doubling teh density just makes it that much better, as it also can double the amt of cache you can provide in application such as FB-DIMMs...allowing the addressing of larger banks, and ultimately leading to larger densities of DRAM avalable through a FB-DIMM sort-of-way. If you double the size of the addressable space, you can also effectively double the bandwidth as well...as I'm still waiting fora 1024-bit bus.
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Old 29th March, 2006, 09:46 AM
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Refresh rates are a necessary evil with DRAM unfortunately. Generally, the lower the refresh rates are, the less the refresh circuitry gets in the way of data access.

FBDIMM has the issue that they're daisy chained. That is, the chipset pushes data out into the first FBDIMM, where it's then clocked through up to seven subsequent FBDIMMs before being passed back to the memory controller. However, FBDIMM is currently a mechanism for implementing standard DDRx memory on a serial bus, thus cutting down the number of interconnects, and hence the cost to manufacture a motherboard.

At the end of the day, the cache on the advanced memory buffer (AMB) is still in the wrong place. By the time the processor has pulled the data from the AMB, it's had to miss the L1 cache, miss the L2 cache, travel through the "memory controller", out over the southbound link, into the AMB, hit the cache in the AMB, back out over the northbound link, across to the "memory controller" before the CPU can even think about doing anything. Unfortunately, due to the daisy chaining nature of FB-DIMM, there is an increased latency.

Quote:
Originally Posted by Micron
Because the channel is based on the point-to-point interconnection of buffer components between FBDIMMs, memory requests are required to travel through N - 1 buffers before reaching the Nth buffer. The result is that a four FBDIMM channel configuration will have greater idle read latency compared to a one FBDIMM channel configuration.
The variable read latency capability can be used to reduce latency for FBDIMMs closer to the host.
It also negates the advantages of putting the memory controller onboard the processors, as technically the memory controller is now on the FBDIMM. This is no big deal for Intel, who don't place the memory controller onboard the CPU anyway. On the other hand, this would negatively affect AMD, as it means decoupling the memory controller from the CPU once again. Is it any wonder that Intel is pushing FBDIMM in the server end of the market?

This may sound negative, but it has a huge impact on systems that need large amounts of memory. You remember the issues that people have with populating four banks of memory, especially on AMD64 based machines? Basically, the memory controller struggles to drive all those lines with such heavy loading on them. With the FB-DIMM, the memory controller never directly drives the DRAM itself. Instead, there are two serial links, one upstream, and one downstream to the nearest AMB. In exactly the same way as RAMBUS, further memory modules are then daisy chained, which allows the AMB to regenerate the signal to massively reduce the risk of errors. The biggest difference between RAMBUS and FB-DIMM, is that RAMBUS embedded the serial link directly on the die of each memory chip. FB-DIMM puts the serial link into the AMB, which then talks to standard DDRx RAM. In some senses, this also decouples the FB-DIMM bus from the type of memory technology in use, so that as long as the FB-DIMM link bandwidth is not exceeded, it doesn't matter if the actual memory technology is DDR, DDR2, DDR3, RAMBUS, z-RAM, MRAM or whatever.

One other benefit is the fact that going from a read operation to a write operation on standard DDR memory incurs waiting for the memory to catch up before the command can be issued. FBDIMM allows the command to be issued, and the AMB then buffers the operation. Of course, this doesn't prevent the problem from actually occuring, but it pushes it down onto the FBDIMM itself, rather than across the memory bus.

The net outcome is that each FBDIMM channel can drive up to eight AMBs. In a dual channel configuration, this could represent as much as 32GB RAM with todays technologies. It also has another massive benefit for 24/7 servers. Due to the way that ABM communicates, and the loopback and reconfigure on the fly capability, it is possible to do a hot remove and hot insert of FBDIMM on a machine. For some (high end) markets, this is a big advantage over having to take a machine down to add or replace memory. Just have to wait for the OS to catch up now.

One thing I have noted is that Intel claim a speed boost (over three times) moving to the FBDIMM architecture. However, they also note this:
Quote:
Originally Posted by Intel
Based on the Dual-Core Intel® Xeon® Processor 5000 sequence (Dempsey)/Blackford chipset with four memory channels each running at 667MHz results in a theoretical throughput of 21.3 GB/s as compared to an Intel® Xeon® Processor with 800MHz FSB with Intel® E7320 chipset with 2 memory channels at 400MHz gives 6.4GB/s theoretical throughput.
I don't know about you, but I consider this to be very deceptive. Four memory channels at 667MHz are faster than two memory channels at 400MHz? That's not really a good comparison. Rough back of the envelope calcuations show that if Intel made a four channel DDR solution that ran the memory bus at 667MHz, it'd be about 3.3 times faster than a two DDR channel solution at 400MHz, which is exactly what they're claiming for FBDIMM.
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Last edited by Áedán; 29th March, 2006 at 10:05 AM.
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Old 29th March, 2006, 10:17 AM
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Ok, back on topic here...

AMD licensed Z-RAM in Janurary this year. Reading between the lines on EETime's article, it suggests that AMD have currently been using SRAM for cache. As we already know, SRAM takes up significantly more space than DRAM. If AMD's tests with Z-RAM prove successful, then they could shrink the current die. Given that Z-RAM takes up approximately 1/5 of the space of SRAM, and that the cache takes up approximately half the space of the processor, it could result in AMD's CPUs almost halving in size. Alternatively, AMD could keep the same size die, and increase the amount of cache five times.

How AMD will deal with the problems with refresh I'm not sure. Given that the capacitance in Z-RAM is significantly smaller than standard DRAM, I suspect that it'd need far more frequent refreshes. Leakage currents related to process shrinks could also cause difficulties with increasing refresh rates. As refreshs block access to memory, it's possible that there would be an increases cache size, but a reduction in the efficiency of the cache. However, all this depends on how AMD implement it!
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