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Old 27th February, 2007, 05:23 AM
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SAMSUNG Speeds Up World's Fastest Graphics Memory

Samsung Electronics Co., Ltd., the world leader in advanced memory technology and the leading producer of high-end graphics memory, announced Friday that it has increased the data transfer speed of the world’s fastest graphics memory - GDDR4 (series four of graphics double-data-rate memory) - by two-thirds. Graphics memory processes video images in desktop PCs, notebooks and workstations to move huge volumes of video simultaneously.

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Old 27th February, 2007, 11:01 AM
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Woohoo!!! Faster video cards FTW!

How long until implementation?
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Old 27th February, 2007, 04:22 PM
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32 Bit bus?
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Old 27th February, 2007, 05:29 PM
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Yes, like most ram currently. 32-bit per IC, x8 chips, gives us 256-bit bus. This is how I knew a long time ago that R600 would be 1gb...memorycontroller was 512bit=16 chips @ 32bit, or 8 chips @ 64-bit. Either way...1gb was teh answer, as only so many IC's are available for such applications.
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Old 27th February, 2007, 05:39 PM
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OK I see. I was a little confused. 2 G Hz Mem...yee haa
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Old 27th February, 2007, 06:10 PM
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LoL. yes there is NO true 256-bit-wide memory bus. only 32-bit. Marketing makes it all sound better tho. Feels good to be lied to, doesn't it?
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Old 27th February, 2007, 07:28 PM
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I always feel lied to any more. lol

Getting quite used to it actually. Everyone claims these things only to find out the truth has been manipulated and stretched to be what they want you to hear.
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Old 27th February, 2007, 09:19 PM
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Quote:
Originally Posted by cadaveca
LoL. yes there is NO true 256-bit-wide memory bus. only 32-bit. Marketing makes it all sound better tho. Feels good to be lied to, doesn't it?
Wait a minute.

You're saying that the R600 only transfers data 4 bytes at a time?
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Old 27th February, 2007, 09:25 PM
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over multiple channels...lol. It's gddr4...not magic.
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Old 28th February, 2007, 12:25 AM
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Ok.

So you're saying, in effect, that it is running 8 channels that are 32 bits wide?

I'm not sure I buy that, but not having seen the internal architectural diagrams, I'm not in a position to argue it.
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Old 28th February, 2007, 01:11 AM
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Actually, if we want it to be exact, it's running 16 channels, 32bits wide. there are 8 nodes each with 2 channels. one channel is not "used", but is still advertized in teh r580 specs, as being 512-bit.

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Orton pegged the floating-point power of today's top Radeon GPUs with 48 pixel shader processors at about 375 gigaflops, with 64 GB/s of memory bandwidth.
Quote:
Beyond just the addition of the arbitration login, ATI are claiming a 4x efficiency in random access of the memory by virtue of the fact there are now 8 memory banks per DRAM on the R520 memory controller, as opposed to 4 banks per DRAM on R420, and also 8x32-bit memory channels rather than 4x64-bit channels. To get the maximum efficiency out of the memory bus the memory channels should ideally carry enough data to max out the width of the channel and the burst length of the DRAM module - the wider the memory channel the less likely this is to occur, so breaking down the memory channel into even smaller width can increase the effective bandwidth utilisation. Up until now all 256-bit memory busses have utilised 4 way crossbar's, breaking the channels down to 4x64-bit busses; its likely that previous designs were not able to go down any further due to the trace density issues mentioned before - the ring bus mechanism now allows this to occur and also reduces the trace density, increasing the clock speeds. Note: the 8x32-bit channels is why we see an odd memory layout on the R520 boards, with one memory chip at angles to the top of the chip; normally 64-bit busses would need to have 32-bit chips paired together.


http://www.beyond3d.com/reviews/ati/r520/index.php?p=05 -Dave Baumann 5 October 2005
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Old 28th February, 2007, 01:40 AM
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Heh.

Glad I didn't try to argue it.

I have to admit that the explanation given doesn't seem to make a lot of sense to me. I'd have to investigate this more to understand what they are saying here.
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Old 28th February, 2007, 02:55 AM
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Just so we are aware, what's runnign through your mind? You've got me curious, as I thought this was a well-known thing.
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Old 28th February, 2007, 03:55 AM
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It very will might be a well known thing today. Bear in mind that it's been on the order of 10 years since I've done serious electronic design, and that was with analog circuitry in power supplies. The last serious digital design I did was 15 years ago, when RAM was still 1-bit wide for the most part, and x8 parts were rare and expensive.

I did a high-speed memory controller cache design for the Motorola 68030 CPU that ran 1 wait-state at a 50 MHz bus speed (in those days that was brutally hard to do), and 4 wait-states to main memory. At that time, everything was getting wider and wider; 64-bit buses were coming, and 128-bit buses were on the drawing board.

So, when I see GPUs specifying 256-bit buses, I assume that means that it transfers 256 bits per cycle. It never even entered my mind that they might be actually running 8 32-bit buses together and calling it a 256-bit bus, or that there would be desireable reasons for doing so.

Thinking about it a bit more, since the internal architecture is basically a 32-bit ALU (if I understand things correctly), I can see where it might make sense to do things that way, though.
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Old 28th February, 2007, 04:41 AM
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uh, yeah...hard to fill a 64-bit bus efficiently with 32-bit programming. Maybe if 64-bit was a bit more common...

even so, going "dual channel" doesn't nessecarily get significant benefits, as seen a la Athlon64. I mean, I guess 15% is alot, but really, it's not when you've "doubled" bus width...

Anyway, sure there's 64, 96, 128 etc busses, but you really have to assume that there's hardware that supports it natively...and far more than the majority of products are still just 32bit, irregardless of the device.
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Old 28th February, 2007, 05:10 AM
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Quote:
Originally Posted by cadaveca
even so, going "dual channel" doesn't nessecarily get significant benefits, as seen a la Athlon64. I mean, I guess 15% is alot, but really, it's not when you've "doubled" bus width...
Right, but in the case of the Athlon64, they aren't claiming that the dual-channel architecture gives them a 128-bit data bus. Running dual channel just lets them transfer data on two channels independently. That's a far different thing than having a "256-bit bus" that is really 8x32-bit.
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Old 28th February, 2007, 05:59 AM
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Better tell that to the mobo makers...
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Old 28th February, 2007, 06:56 AM
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Oh my......
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Old 28th February, 2007, 03:54 PM
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lol. It's a bad situation, for sure, IMHO, but it's the way it is. Every single one of my intel boards claims a 128-bit bus for mem...but it's 64-bit, dualchannel. Just power the board up, and it's there...
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