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GlobalFoundries Outlines 22 nm Roadmap David Lammers, News Editor -- Semiconductor International, 7/28/2009 GlobalFoundries (Sunnyvale, Calif.) plans to apply embedded silicon carbon (eSiC) stressors on its 22 nm nFET transistors, and is likely to use through-silicon vias (TSVs) to connect a fast SOI-based DRAM layer to a logic die, said John Pellerin, director of technology development at the IBM/GlobalFoundries Alliance in Fishkill, N.Y. Read more on the Front Page: AOA - GlobalFoundries Outlines 22 nm Roadmap |
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amd , embedded silicon carbide , esic , globalfoundaries , ibm |
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