under-volt to test for EM?

[drow_elf]

i was just wondering... you know how you can almost never tell that electromigration is occuring till it happens? i was wondering if you could do a "poor mans test" for EM by first establishing a baseline of lowest stable V (how low can you go at stock freq.) then after OCing (and thus increasing voltage) for a good while seeing if you can go back to the same setting.  if you were able go back to that same low voltage your cpu hasnt experenced signifigant EM over the test period BUT if you had to set a higher voltage then you have had at least some EM occur. i believe the reason being that if EM were occuring the defects that develop would hinder the CPU much more at low voltages

so am i right? (c'mon experts! stress those little brain cells!) i'm probably not...

[Áedán]

EM is a gradual process. How long do you give the chip before you test it for possible EM side effects.?

In addition, once EM has started to spread between the junctions, it can continue, even if you've brought the chip back into specs. This is because the junctions have become more sensitive to further damage. Then it's too late, even if you revert back to stock speeds.

I have a sneaking suspicion that in some circumstances, the EM can make junctions more sensitive (as there's less gap).

Static electricity also helps EM greatly. If you're really lucky with static and CMOS chips, you can blow (literally) nice holes in the MO layer.

AidanII

[drow_elf]

so if the EM was forming a hillock (i think thats the right word) in the junction you would (maybe) be able to run it at a lower voltage than before? didnt think of that...

how do they test for em in the big, bad, real world? anything i can think of would involve using a clean room, exposing, the core and looking at it under a big microscope (or maybe one of those machines that find dust on the silicon wafers)